The present invention generally relates to an arithmetic operation processor for performing such operation as arithmetic operation and, more particularly, to a parallel processing type central processing apparatus which can be suitably used in such applications that can realize high-speed arithmetic operation.
An arithmetic operation processing apparatus is disclosed in U.S. Pat. No. 4,956,800 titled "ARITHMETIC OPERATION PROCESSING APPARATUS OF THE PARALLEL PROCESSING TYPE AND COMPILER WHICH IS USED IN THIS APPARATUS", issued Sep. 11, 1990 to Kametani, in which a plurality of CPUs are operated based on macro instructions, and the disclosure of which is incorporated herein by reference.
Also disclosed in JP-A-63-316133 is an arithmetic operation processing apparatus which comprises a macro instruction sequence processor and a host processor.
In order to enhance the real time processing ability and scalar processing ability in the prior art, there has been proposed an arithmetic operation processing apparatus which comprises a host processor, an arithmetic operation unit for performing arithmetic operation and a second processor for executing the arithmetic operational sequence of the arithmetic operation unit described on the host processor, wherein the host and second processors share the arithmetic operation unit to cause the second processor to execute the arithmetic operational sequence and concurrently therewith to cause the host processor to perform data inputting and outputting operations between a main memory and the register file of the arithmetic operation unit, whereby the parallel processing ability or parallelism of the hardware is effectively enhanced and the high speed arithmetic operation processing is realized.
The above prior art is excellent in the highspeed arithmetic operation processing, but in the prior art, sufficient consideration is not paid to the efficiency of the parallel processing operation when a multiplicity of processors are operated as if they were a single processor.